In a semiconductor integrated circuit, a multi-bit flip-flop is used. The multi-bit flip-flop includes a plurality of flip-flops. The plurality of flip-flops share one clock buffer. Hence, in the multi-bit flip-flop, the number of clock buffers can be decreased, and the circuit area and power consumption can be reduced.
On the other hand, as a test method (failure analysis) of the semiconductor integrated circuit, a scan test method is used. In the scan test, the plurality of flip-flops in the multi-bit flip-flop are electrically coupled as a parallel type or serial type scan chain.
In the parallel type, a scan test data signal is input to the scan input terminal of the flip-flop of each bit in the multi-bit flip-flop. The scan test data signal is output to the scan output terminal of the flip-flop of each bit. That is, the scan test is executed using the scan test data signal output from the scan output terminal of the flip-flop of each bit.
In the serial type, a scan test data signal is input to the scan input terminal of the flip-flop of the first bit (first stage) in the multi-bit flip-flop and output from the scan output terminal. Then, the scan test data signal is input to the scan input terminal of the flip-flop of the second bit. When the scan test data signal is output from the scan output terminal of the flip-flop of the second bit, the scan test data signal is input to the scan input terminal of the flip-flop of the third bit. In a similar manner, the scan test data signal is input to the scan input terminal of the flip-flop of the final bit and output from the scan output terminal. The scan test is executed using the scan test data signal output from the scan output terminal of the flip-flop of the final bit.
In the scan test of the serial type, since a logic circuit or a long wire is electrically coupled to the scan output terminal of each flip-flop in the multi-bit flip-flop, there is the influence of a load capacity and the like. In this case, the scan test data signal from the scan output terminal of each flip-flop changes its waveform and is then input to the scan input terminal of the next flip-flop. As a result, the reliability of the scan test lowers.
Additionally, to suppress the influence of the load capacity, a new buffer circuit or the like is necessary. In this case, the circuit area increases.